// sdr.v


`timescale 1 ps / 1 ps
module sdr (
		input  wire [24:0] sdr_address,       //   sdr.address
		input  wire        sdr_byteenable_n,  //      .byteenable_n
		input  wire        sdr_chipselect,    //      .chipselect
		input  wire [7:0]  sdr_writedata,     //      .writedata
		input  wire        sdr_read_n,        //      .read_n
		input  wire        sdr_write_n,       //      .write_n
		output wire [7:0]  sdr_readdata,      //      .readdata
		output wire        sdr_readdatavalid, //      .readdatavalid
		output wire        sdr_waitrequest,   //      .waitrequest
		output wire [12:0] inout_addr,        // inout.addr
		output wire        inout_cke,         //      .cke
		output wire        inout_we_n,        //      .we_n
		output wire        inout_dqm,         //      .dqm
		output wire [1:0]  inout_ba,          //      .ba
		output wire        inout_cs_n,        //      .cs_n
		output wire        inout_cas_n,       //      .cas_n
		inout  wire [7:0]  inout_dq,          //      .dq
		output wire        inout_ras_n,       //      .ras_n
		input  wire        clk_clk,           //   clk.clk
		input  wire        clk_1_reset_n      // clk_1.reset_n
	);

	wire    rst_controller_reset_out_reset; // rst_controller:reset_out -> sdram_0:reset_n

	sdr_sdram_0 sdram_0 (
		.clk            (clk_clk),                         //   clk.clk
		.reset_n        (~rst_controller_reset_out_reset), // reset.reset_n
		.az_addr        (sdr_address),                     //    s1.address
		.az_be_n        (sdr_byteenable_n),                //      .byteenable_n
		.az_cs          (sdr_chipselect),                  //      .chipselect
		.az_data        (sdr_writedata),                   //      .writedata
		.az_rd_n        (sdr_read_n),                      //      .read_n
		.az_wr_n        (sdr_write_n),                     //      .write_n
		.za_data        (sdr_readdata),                    //      .readdata
		.za_valid       (sdr_readdatavalid),               //      .readdatavalid
		.za_waitrequest (sdr_waitrequest),                 //      .waitrequest
		.zs_addr        (inout_addr),                      //  wire.export
		.zs_ba          (inout_ba),                        //      .export
		.zs_cas_n       (inout_cas_n),                     //      .export
		.zs_cke         (inout_cke),                       //      .export
		.zs_cs_n        (inout_cs_n),                      //      .export
		.zs_dq          (inout_dq),                        //      .export
		.zs_dqm         (inout_dqm),                       //      .export
		.zs_ras_n       (inout_ras_n),                     //      .export
		.zs_we_n        (inout_we_n)                       //      .export
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS        (1),
		.OUTPUT_RESET_SYNC_EDGES ("deassert"),
		.SYNC_DEPTH              (2)
	) rst_controller (
		.reset_in0  (~clk_1_reset_n),                 // reset_in0.reset
		.clk        (clk_clk),                        //       clk.clk
		.reset_out  (rst_controller_reset_out_reset), // reset_out.reset
		.reset_in1  (1'b0),                           // (terminated)
		.reset_in2  (1'b0),                           // (terminated)
		.reset_in3  (1'b0),                           // (terminated)
		.reset_in4  (1'b0),                           // (terminated)
		.reset_in5  (1'b0),                           // (terminated)
		.reset_in6  (1'b0),                           // (terminated)
		.reset_in7  (1'b0),                           // (terminated)
		.reset_in8  (1'b0),                           // (terminated)
		.reset_in9  (1'b0),                           // (terminated)
		.reset_in10 (1'b0),                           // (terminated)
		.reset_in11 (1'b0),                           // (terminated)
		.reset_in12 (1'b0),                           // (terminated)
		.reset_in13 (1'b0),                           // (terminated)
		.reset_in14 (1'b0),                           // (terminated)
		.reset_in15 (1'b0)                            // (terminated)
	);

endmodule
